Electronic packages are widely used in a variety of well-known applications from computers to computer controls of a wide variety of devices, for example, automobiles and home appliances, among others. Electronic packages for complex systems typically are comprised of interconnected integrated circuit chips. The integrated circuit chips are usually made from a semiconductor material such as silicon or gallium arsenide. Microscopic circuits are formed in the various layers of the integrated circuit chips using known photolithographic techniques. The integrated circuit chips may be mounted in a package which may then mounted on a printed circuit board. Electronic packages including integrated circuit chips typically have numerous external pads which are mechanically attached by solder or a variety of other known techniques to conductor patterns on the printed circuit board.
Typically, the package on which these integrated semiconductor chips are mounted includes a substrate or other chip mounting device. One example of such a substrate is a leadframe. High performance leadframes typically include at least an area on which a semiconductor integrated chip is mounted and a plurality of power, ground, and or signal planes or layers to which power, ground, and/or signal sites of the integrated semiconductor chip are electrically attached. A semiconductor integrated chip may be attached to the leadframe using adhesive or other techniques for attaching such a chip to a leadframe which are commonly known to those skilled in the art, such as soldering. The power, ground, and signal sites on the chip may then be electrically connected to selected power, ground, and signal planes or layers by wires.
Once a semiconductor chip is attached to the leadframe and the electrical connections to the leadframe made, the leadframe may be enclosed or encapsulated in a protective enclosure. Such enclosures may include encapsulation in plastic or a multi-part housing made of plastic, ceramic, or metal or combinations, thereof. The enclosure may protect the leadframe and the attached chip from physical, electrical, and/or chemical damage. The leadframe and attached chip may then be mounted on, for example, a printed circuit board or card, preferably by a plurality of solder connections or joints. The printed circuit board or card may then be incorporated into a wide variety of devices such as computers, automobiles, appliances, among others.
FIG. 1A shows a much enlarged bottom view of a portion of a prior art electronic package 10. FIG. 1B shows a much enlarged view, in elevation of the portion of prior art electronic package 10 taken along line 1B—1B in FIG. 1A. Referring to FIG. 1B, package 10 includes a ground layer 12 having an upper section 14 and a lower section 16 and a semiconductor chip 18. The semiconductor chip 18 has a first surface 20 and a second surface 22. A first conductive pad 24 on second surface 22 of semiconductor chip 18 is electrically connected to upper section 14 of ground layer 12 by wire 26 (ground wire). A second conductive pad 28 on second surface 22 of semiconductor chip 18 is electrically connected to a conductive signal layer 30 by another wire 32 (signal wire). A first solder connection 34 (shown in phantom) electrically and mechanically connects ground layer 12 with a printed circuit board 36 (shown in phantom). A second solder connection 38 (shown in phantom) electrically and mechanically connects conductive signal layer 30 with printed circuit board 36. Electronic package 10 accommodates a standard semiconductor chip having the maximum size allowed in the industry.
FIG. 1C shows a much enlarged bottom view of a portion of another prior art electronic package 11. FIG. 1D shows a much enlarged view, in elevation of the portion of prior art electronic package 11 taken along line 1D—1D in FIG. 1C. Referring to FIG. 1D, package 11 includes a ground layer 13 having an upper section 15 and a lower section 17 and a semiconductor chip 19. The semiconductor chip 19 has a first surface 21 and a second surface 23. A first conductive pad 25 on second surface 23 of semiconductor chip 19 is electrically connected to upper section 15 of ground layer 13 by wire 27 (ground wire). A second conductive pad 29 on second surface 23 of semiconductor chip 19 is electrically connected to a conductive signal layer 31 by another wire 33 (signal wire). A first solder connection 35 (shown in phantom) electrically and mechanically connects ground layer 13 with a printed circuit board 37 (shown in phantom). A second solder connection 39 (shown in phantom) electrically and mechanically connects conductive signal layer 31 with printed circuit board 37. In wirebonded packages, for performance reasons, it is important to design packages with the shortest length of wires possible. Shorter wires yield smaller inductances. In this prior art package, the package has been customized for a small semiconductor chip by designing upper section 15 closer to semiconductor chip 19 than in electronic package 10 to minimize the length of wire 27. This results in a reduced area 17 available to be soldered by solder connection 35 to printed circuit board 37. During process handling of electronic package 11 stresses can be generated in first solder connection 35 and second solder connection 39. Stresses can be generated in these solder connections during assembly of other components (not shown) on printed circuit board 37. During operation of electronic package 11, mounted on printed circuit board 37, stresses are generated in first solder connection 35 and second solder connection 39 caused by a mismatch in the coefficient of thermal expansion (CTE) between electronic package 11 and printed circuit board 37. These handling, assembly, and CTE stresses can cause first solder connection 35 and/or second solder connection 39 to prematurely fail affecting both product cost (lower yields) and reliability. Furthermore, signal wire 33 is very long relative to wire 27 and has marginally poor signal inductance.
Thus it is desirable to have an electronic package that substantially inhibits or prevents cracking of the first solder connection caused by handling, assembly, or field operation. It is also desirable to have an electronic package which has a shorter signal wire and resultantly improved performance (lower signal inductance) during operation. Packages of this type will have improved yield, improved performance and increased operation field life.